? semiconductor components industries, llc, 2005 november, 2005 ? rev. 9 1 publication order number: MC10EL34/d MC10EL34, mc100el34 5vecl 2, 4, 8 clock generation chip description the mc10/100el34 is a low skew 2, 4, 8 clock generation chip designed explicitly for low skew clock generation applications. the internal dividers are synchronous to each other, therefore, the common output edges are all precisely aligned. the v bb pin, an internally generated voltage supply, is available to this device only. for single-ended input conditions, the unused differential input is connected to v bb as a switching reference voltage. v bb may also rebias ac coupled inputs. when used, decouple v bb and v cc via a 0.01 f capacitor and limit current sourcing or sinking to 0.5 ma. when not used, v bb should be left open. the common enable (en ) is synchronous so that the internal dividers will only be enabled/disabled when the internal clock is already in the low state. this avoids any chance of generating a runt clock pulse on the internal clock when the device is enabled/disabled as can happen with an asynchronous control. an internal runt pulse could lead to losing synchronization between the internal divider stages. the internal enable flip ? flop is clocked on the falling edge of the input clock, therefore, all associated specification limits are referenced to the negative edge of the clock input. upon startup, the internal flip-flops will attain a random state; the master reset (mr) input allows for the synchronization of the internal dividers, as well as multiple el34s in a system. the 100 series contains temperature compensation. features ? 50 ps output-to-output skew ? synchronous enable/disable ? master reset for synchronization ? pecl mode operating range: v cc = 4.2 v to 5.7 v with v ee = 0 v ? necl mode operating range: v cc = 0 v with v ee = ? 4.2 v to ? 5.7 v ? internal input 75 k pulldown resistors on clk(s), en , and mr ? pb ? free packages are available* *for additional information on our pb ? free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. so ? 16 d suffix case 751b 1 16 marking diagrams* 1 16 10el34g awlyww a = assembly location wl = wafer lot yy = year ww = work week g= pb ? free package 1 16 100el34g awlyww http://onsemi.com *for additional marking information, refer to application note and8002/d. see detailed ordering and shipping information in the package dimensions section on page 7 of this data sheet. ordering information
MC10EL34, mc100el34 http://onsemi.com 2 v cc figure 1. logic diagram and pinout assignment q0 q1 v cc q2 15 16 14 13 12 11 10 2 1 3 4 56 7 v cc 9 8 q2 q0 en nc clk clk v bb mr v ee d qr qr 2 qr 4 qr 8 q1 *all v cc pins are tied together on the die. warning: all v cc and v ee pins must be externally connected to power supply to guarantee proper operation. table 1. function table clk* en * mr * function z zz x l h x l l h divide hold q 0 ? 3 reset q 0 ? 3 *pins will default low when left open. z = low-to-high transition zz = high-to-low transition table 2. pin description pin function clk, clk ecl diff clock inputs en ecl sync enable mr ecl master reset q0, q0 ecl diff 2 outputs q1, q1 ecl diff 4 outputs q2, q2 ecl diff 8 outputs v bb reference voltage output v cc positive supply v ee negative supply nc no connect table 3. attributes characteristics value internal input pulldown resistor 75 k internal input pullup resistor n/a esd protection human body model machine model charge device model > 1 kv > 100 v > 2 kv moisture sensitivity (note 1) level 1 flammability rating oxygen index: 28 to 34 ul 94 v ? 0 @ 0.125 in transistor count 191 devices meets or exceeds jedec spec eia/jesd78 ic latchup test 1. for additional moisture sensitivity information, refer to application note and8003/d.
MC10EL34, mc100el34 http://onsemi.com 3 table 4. maximum ratings symbol parameter condition 1 condition 2 rating unit v cc pecl mode power supply v ee = 0 v 8 v v ee necl mode power supply v cc = 0 v ? 8 v v i pecl mode input voltage necl mode input voltage v ee = 0 v v cc = 0 v v i v cc v i v ee 6 ? 6 v v i out output current continuous surge 50 100 ma ma i bb v bb sink/source 0.5 ma t a operating temperature range ? 40 to +85 c t stg storage temperature range ? 65 to +150 c ja thermal resistance (junction ? to ? ambient) 0 lfpm 500 lfpm so ? 16 so ? 16 130 75 c/w c/w jc thermal resistance (junction ? to ? case) standard board so ? 16 33 to 36 c/w t sol wave solder pb pb ? free <2 to 3 sec @ 248 c <2 to 3 sec @ 260 c 265 265 c maximum ratings are those values beyond which device damage can occur. maximum ratings applied to the device are individual str ess limit values (not normal operating conditions) and are not valid simultaneously. if these limits are exceeded, device functional operation i s not implied, damage may occur and reliability may be affected. table 5. 10el series pecl dc characteristics v cc = 5.0 v; v ee = 0 v (note 2) symbol characteristic ? 40 c 25 c 85 c unit min typ max min typ max min typ max i ee power supply current 39 39 39 ma v oh output high voltage (note 3) 3920 4010 4110 4020 4105 4190 4090 4185 4280 mv v ol output low voltage (note 3) 3050 3200 3350 3050 3210 3370 3050 3227 3405 mv v ih input high voltage (single ? ended) 3770 4110 3870 4190 3940 4280 mv v il input low voltage (single ? ended) 3050 3500 3050 3520 3050 3555 mv v bb output voltage reference 3.57 3.7 3.65 3.75 3.69 3.81 v v ihcmr input high voltage common mode range (differential) (note 4) 3.0 4.6 3.0 4.6 3.0 4.6 v i ih input high current 150 150 150 a i il input low current 0.5 0.5 0.3 a note: device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printe d circuit board with maintained transverse airflow greater than 500 lfpm. electrical parameters are guaranteed only over the declared operating temperature range. functional operation of the device exceeding these conditions is not implied. device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 2. input and output parameters vary 1:1 with v cc . v ee can vary +0.06 v / ? 0.5 v. 3. outputs are terminated through a 50 resistor to v cc ? 2.0 v. 4. v ihcmr min varies 1:1 with v ee , v ihcmr max varies 1:1 with v cc . the v ihcmr range is referenced to the most positive side of the differential input signal. normal operation is obtained if the high level falls wi thin the specified range and the peak-to-peak voltage lies betwe en v pp min and 1 v.
MC10EL34, mc100el34 http://onsemi.com 4 table 6. 10el series necl dc characteristics v cc = 0 v; v ee = ? 5.0 v (note 5) symbol characteristic ? 40 c 25 c 85 c unit min typ max min typ max min typ max i ee power supply current 39 39 39 ma v oh output high voltage (note 6) ? 1080 ? 990 ? 890 ? 980 ? 895 ? 810 ? 910 ? 815 ? 720 mv v ol output low voltage (note 6) ? 1950 ? 1800 ? 1650 ? 1950 ? 1790 ? 1630 ? 1950 ? 1773 ? 1595 mv v ih input high voltage (single ? ended) ? 1230 ? 890 ? 1130 ? 810 ? 1060 ? 720 mv v il input low voltage (single ? ended) ? 1950 ? 1500 ? 1950 ? 1480 ? 1950 ? 1445 mv v bb output voltage reference ? 1.43 ? 1.30 ? 1.35 ? 1.25 ? 1.31 ? 1.19 v v ihcmr input high voltage common mode range (differential) (note 7) ? 2.0 ? 0.4 ? 2.0 ? 0.4 ? 2.0 ? 0.4 v i ih input high current 150 150 150 a i il input low current 0.5 0.5 0.3 a note: device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printe d circuit board with maintained transverse airflow greater than 500 lfpm. electrical parameters are guaranteed only over the declared operating temperature range. functional operation of the device exceeding these conditions is not implied. device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 5. input and output parameters vary 1:1 with v cc . v ee can vary +0.06 v / ? 0.5 v. 6. outputs are terminated through a 50 resistor to v cc ? 2.0 v. 7. v ihcmr min varies 1:1 with v ee , v ihcmr max varies 1:1 with v cc . the v ihcmr range is referenced to the most positive side of the differential input signal. normal operation is obtained if the high level falls wi thin the specified range and the peak-to-peak voltage lies betwe en v pp min and 1 v. table 7. 100el series pecl dc characteristics v cc = 5.0 v; v ee = 0 v (note 8) symbol characteristic ? 40 c 25 c 85 c unit min typ max min typ max min typ max i ee power supply current 39 39 42 ma v oh output high voltage (note 9) 3915 3995 4120 3975 4045 4120 3975 4050 4120 mv v ol output low voltage (note 9) 3170 3305 3445 3190 3295 3380 3190 3295 3380 mv v ih input high voltage (single ? ended) 3835 4120 3835 4120 3835 4120 mv v il input low voltage (single ? ended) 3190 3525 3190 3525 3190 3525 mv v bb output voltage reference 3.62 3.74 3.62 3.74 3.62 3.74 v v ihcmr input high voltage common mode range (differential configuration) (note 10) 2.2 4.6 2.2 4.6 2.2 4.6 v i ih input high current 150 150 150 a i il input low current 0.5 0.5 0.5 a note: device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printe d circuit board with maintained transverse airflow greater than 500 lfpm. electrical parameters are guaranteed only over the declared operating temperature range. functional operation of the device exceeding these conditions is not implied. device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 8. input and output parameters vary 1:1 with v cc . v ee can vary +0.8 v / ? 0.5 v. 9. outputs are terminated through a 50 resistor to v cc ? 2.0 v. 10. v ihcmr min varies 1:1 with v ee , v ihcmr max varies 1:1 with v cc . the v ihcmr range is referenced to the most positive side of the differential input signal. normal operation is obtained if the high level falls wi thin the specified range and the peak-to-peak voltage lies betwe en v pp min and 1 v.
MC10EL34, mc100el34 http://onsemi.com 5 table 8. 100el series necl dc characteristics v cc = 0 v; v ee = ? 5.0 v (note 11) symbol characteristic ? 40 c 25 c 85 c unit min typ max min typ max min typ max i ee power supply current 39 39 42 ma v oh output high voltage (note 12) ? 1085 ? 1005 ? 880 ? 1025 ? 955 ? 880 ? 1025 ? 955 ? 880 mv v ol output low voltage (note 12) ? 1830 ? 1695 ? 1555 ? 1810 ? 1705 ? 1620 ? 1810 ? 1705 ? 1620 mv v ih input high voltage (single ? ended) ? 1165 ? 880 ? 1165 ? 880 ? 1165 ? 880 mv v il input low voltage (single ? ended) ? 1810 ? 1475 ? 1810 ? 1475 ? 1810 ? 1475 mv v bb output voltage reference ? 1.38 ? 1.26 ? 1.38 ? 1.26 ? 1.38 ? 1.26 v v ihcmr input high voltage common mode range (differential configuration) (note 13) ? 2.8 ? 0.4 ? 2.8 ? 0.4 ? 2.8 ? 0.4 v i ih input high current 150 150 150 a i il input low current 0.5 0.5 0.5 a note: device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printe d circuit board with maintained transverse airflow greater than 500 lfpm. electrical parameters are guaranteed only over the declared operating temperature range. functional operation of the device exceeding these conditions is not implied. device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 11. input and output parameters vary 1:1 with v cc . v ee can vary +0.8 v / ? 0.5 v. 12. outputs are terminated through a 50 resistor to v cc ? 2.0 v. 13. v ihcmr min varies 1:1 with v ee , v ihcmr max varies 1:1 with v cc . the v ihcmr range is referenced to the most positive side of the differential input signal. normal operation is obtained if the high level falls wi thin the specified range and the peak-to-peak voltage lies betwe en v pp min and 1 v. table 9. ac characteristics v cc = 5.0 v; v ee = 0.0 v or v cc = 0.0 v; v ee = ? 5.0 v (note 14) symbol characteristic ? 40 c 25 c 85 c unit min typ max min typ max min typ max f max maximum toggle frequency 1.1 1.1 1.1 ghz t plh t phl propagation clk to q0 delay to clk to q1,2 output mr to q 960 900 750 1200 1140 1060 960 900 750 1200 1140 1060 970 910 790 1210 1150 1090 ps t skew within-device skew (note 15) 100 100 100 ps t jitter cycle ? to ? cycle jitter 1.0 1.0 1.0 ps t s setup time en 400 400 400 ps t h hold time en 250 250 250 ps t rr set/reset recovery 400 200 400 200 400 200 ps v pp input swing (note 16) 150 1000 150 1000 150 1000 mv t r t f output rise/fall times q (20% ? 80%) 225 475 225 475 225 475 ps note: device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printe d circuit board with maintained transverse airflow greater than 500 lfpm. electrical parameters are guaranteed only over the declared operating temperature range. functional operation of the device exceeding these conditions is not implied. device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 14. 10 series: v ee can vary +0.06 v / ? 0.5 v. 100 series: v ee can vary +0.8 v / ? 0.5 v. 15. within-device skew is defined as identical transitions on similar paths through a device. 16. v pp min is minimum input swing for which ac parameters guaranteed. the device has a dc gain of 40.
MC10EL34, mc100el34 http://onsemi.com 6 there are two distinct functional relationships between the master reset and clock: case 1: if the mr is de ? asserted (h ? l), while the clock is still high, the outputs will follow the first ensuing clock rising edge. the en signal will ?freeze? the internal divider flip ? flops on the first falling edge of clk after its assertion. the internal divider flip ? flops will maintain their state during the freeze. the en is deasserted (low), and after the next falling edge of clk, then the internal divider flip ? flops will ?unfreeze? and continue to their next state count with proper phase rela- tionships. case 2: if the mr is de ? asserted (h ? l), after the clock has transitioned low, the outputs will follow the second ensuing clock rising edge. case 1 case 2 figure 2. timing diagrams clock output mr t rr clock output mr t rr figure 3. reset recovery time clk q0 q1 q2 en internal clock disabled internal clock enabled mr clk q0 q1 q2 en internal clock disabled internal clock enabled mr
MC10EL34, mc100el34 http://onsemi.com 7 figure 4. typical termination for output driver and device evaluation (see application note and8020/d ? termination of ecl logic devices.) driver device receiver device qd q d z o = 50 z o = 50 50 50 v tt v tt = v cc ? 2.0 v ordering information device package shipping ? MC10EL34d so ? 16 48 units / rail MC10EL34dg so ? 16 (pb ? free) 48 units / rail MC10EL34dr2 so ? 16 2500 / tape & reel MC10EL34dr2g so ? 16 (pb ? free) 2500 / tape & reel mc100el34d so ? 16 48 units / rail mc100el34dg so ? 16 (pb ? free) 48 units / rail mc100el34dr2 so ? 16 2500 / tape & reel mc100el34dr2g so ? 16 (pb ? free) 2500 / tape & reel ?for information on tape and reel specifications, including part orientation and tape sizes, please refer to our tape and reel packaging specifications brochure, brd8011/d. resource reference of application notes an1405/d ? ecl clock distribution techniques an1406/d ? designing with pecl (ecl at +5.0 v) an1503/d ? eclinps i/o spice modeling kit an1504/d ? metastability and the eclinps family an1568/d ? interfacing between lvds and ecl an1642/d ? the ecl translator guide and8001/d ? odd number counters design and8002/d ? marking and date codes and8020/d ? termination of ecl logic devices and8066/d ? interfacing with eclinps and8090/d ? ac characteristics of ecl devices
MC10EL34, mc100el34 http://onsemi.com 8 package dimensions so ? 16 d suffix case 751b ? 05 issue j notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. dimensions a and b do not include mold protrusion. 4. maximum mold protrusion 0.15 (0.006) per side. 5. dimension d does not include dambar protrusion. allowable dambar protrusion shall be 0.127 (0.005) total in excess of the d dimension at maximum material condition. 18 16 9 seating plane f j m r x 45 g 8 pl p ? b ? ? a ? m 0.25 (0.010) b s ? t ? d k c 16 pl s b m 0.25 (0.010) a s t dim min max min max inches millimeters a 9.80 10.00 0.386 0.393 b 3.80 4.00 0.150 0.157 c 1.35 1.75 0.054 0.068 d 0.35 0.49 0.014 0.019 f 0.40 1.25 0.016 0.049 g 1.27 bsc 0.050 bsc j 0.19 0.25 0.008 0.009 k 0.10 0.25 0.004 0.009 m 0 7 0 7 p 5.80 6.20 0.229 0.244 r 0.25 0.50 0.010 0.019 on semiconductor and are registered trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to mak e changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for an y particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including wi thout limitation special, consequential or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/or specifications can and do vary in different application s and actual performance may vary over time. all operating parameters, including ?typicals? must be validated for each customer application by customer?s technical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scillc and its of ficers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, direct ly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in any manner. publication ordering information n. american technical support : 800 ? 282 ? 9855 toll free usa/canada japan : on semiconductor, japan customer focus center 2 ? 9 ? 1 kamimeguro, meguro ? ku, tokyo, japan 153 ? 0051 phone : 81 ? 3 ? 5773 ? 3850 MC10EL34/d eclinps are registered trademarks of semiconductor components industries, llc (scillc). literature fulfillment : literature distribution center for on semiconductor p.o. box 61312, phoenix, arizona 85082 ? 1312 usa phone : 480 ? 829 ? 7710 or 800 ? 344 ? 3860 toll free usa/canada fax : 480 ? 829 ? 7709 or 800 ? 344 ? 3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : http://onsemi.com order literature : http://www.onsemi.com/litorder for additional information, please contact your local sales representative.
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